Not applicable.
1. Field of the Invention
The invention relates to a memory buffer architecture, and more particularly to memory read operations with prefetching to a buffer.
2. Description of the Related Art
Many systems contain random access memory, or RAM, to provide temporary storage of data when a system is powered up. A source within the system, often known as a master, will typically read from the RAM or write to the RAM. To illustrate, a processor in a system may be a master. Because a master controls the bus which connects between the master and the RAM to access the RAM, the master is also commonly known as a bus owner or bus master during the time. Also found in many systems is an interface to the memory, or RAM, known as a RAM controller. So, for example, in a system using dynamic RAM, or DRAM, a DRAM controller may interface between the master and the DRAM itself.
In addition, DRAM controllers have been provided which operate at a different frequency than the master device. Along with presenting various timing issues, setup/hold time issues for example, the different operating frequencies require the faster device to experience inefficient time out periods or idle states. For example, a DRAM controller that is operating at a higher frequency than the CPU, may need to sit idle during some CPU clock cycles so that the CPU read operations can catch up. These wait states have been avoided by using a variety of techniques, including page-mode memory, interleaved memory, burst modes, and memory caches.
There are a number of techniques for implementing burst modes. In a data bus, for example, a burst mode usually is implemented by allowing a device to seize control of the bus and not permitting other devices to interrupt. In a CPU, burst mode operation has been implemented by blindly retrieving memory data in addition to the data immediately requested. The additional memory data is then stored within CPU local memory for reading at a later time.
The computer system provides improved performance for data operations. A memory controller having a read buffer that receives and stores request information is provided between multiple requesting master devices and a memory device. The read buffer is capable of operation in either a demand read mode or a prefetch read mode. In the demand mode, the read buffer immediately forwards data to the requesting master. A full cache line of data containing the requested data is concurrently stored in the read buffer such that subsequent read requests from the same or other requesting devices that matches either the previously requested data or data within the stored cache line of data in the read buffer is supplied to the requesting master in zero wait states. Read prefetch is supported by receiving and storing additional data from memory. The prefetch data is retrieved without an immediate need for that data. Performance of read operations is increased in that any subsequent read request matching either the previously demanded data or the prefetched data causes the matching data to be provided to the requesting master in zero wait states without additional memory access.